Consortium launches CXL 3.0 CPU Interconnect based on PCIe 6.0 – Computer – News

The CXL Consortium has released version 3.0 of its Compute Express Link. The group released specifications for this bonding standard on Tuesday. CXL makes it possible to connect CPUs and accelerators, among other things.

CXL 3.0 will receive support, among other things For the PCIe 6.0 standard, which provides a maximum bandwidth of 64 Gb / s, which is up to 128 Gb / s for the x16 interface. This is double the previous versions of CXL, which were all based on PCIe 5.0. This was achieved by transferring PCIe to pam4-Signaling. CXL 3.0 also uses files new flashWith a larger packet size of 256 bytes to reduce latency, just like PCIe 6.0 itself. According to the consortium, the latency was not increased compared to CXL 2.0 as a result.

Aside from the higher bandwidth, CXL 3.0 gets better too one to oneCommunication between devices. From now on, devices can access each other’s memory directly, without host interference. Improved memory pooling also allows multiple hosts to access a memory pool at the same time. It is also possible to connect several switches to each other. Previously, it was only possible to place a single switch between the host and its devices.

CXL is an open standard based on PCIe that serves as an interface between CPUs, GPUs, FPGAs, network devices, memory such as DDR4 and DDR5, and storage. In doing so, the standard cache consistency between those devices. CXL is primarily designed for data centers and is also suitable for connecting multiple servers. For example, CXL 3.0 supports up to 4,096 different nodes.

The CXL Consortium is supported by major chip companies such as AMD, Arm, Intel, Micron, Nvidia, and Samsung. For example, AMD’s upcoming Epyc server chips and Intel Sapphire Rapids processors will receive support for the CXL 1.1 specification. Tech companies like Google, Meta, and Microsoft also support the standard.

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