Imec has successfully imaged the first logical and dramatic structures on a chip using ASML’s high-NA-EUV device. This happened in the joint ASML-IMEC laboratory. These new UV machines are expected to be available for mass production next year.
I have emc Different types of patterns It depicts With ASML’s new high NA device. According to imec CEO, Luuk van den Hove, the results confirm the “long-expected” resolution capabilities of high NA EUV lithography, with Throw From less than 20 nanometers. This would make it possible to image smaller transistors using a single transistor. ExposureThe imec prints won’t actually be used in chips that come to market, but they mainly demonstrate the potential performance of ASML’s new tools.
The Belgian research foundation has, among other things, a random LogicThe patterns were imaged as metallic lines with a density of 9.5 nanometers. This corresponds to a pitch of 19 nanometers. This pitch represents the distance between the structures on the chip. The company also imaged them randomly. Via off, with Center to center– 30nm spacing and “excellent” precision and uniformity. Vias are electronic connections between metal layers inside the chip. Imec also speaks of 2D features with 22nm precision and good performance. In addition to logic patterns, the research institute was also able to image a structure specifically designed for DRAM chips.
From left to right: logical metal lines with 19nm pitch, 30nm pitch, 2D features and drama structure. Source: IMK
High-NA will be the next generation of ASML’s UV lithography technology. These new devices will have a larger numerical aperture of 0.55 instead of 0.33. This makes it possible to display smaller features and place them closer together, allowing chipmakers to make smaller transistors.
Imec cartridges have already shown a temperature of 19nm. The theoretical limit for high NA is 16nm, while with current UV devices it is 26nm. The switch should prevent chipmakers from Multiple decoration It must be diffused. A layer of the wafer is exposed to UV plasma multiple times to enable smaller transistors. However, this also makes the production process more expensive and increases the risk of production errors.
ASML has been working on high-NA EUV for years. The first testbed was delivered to Intel late last year. In June, ASML and IMEC opened a high-NA lab in Veldhoven, where the companies can conduct research with chipmakers on how to use high-NA in practice. ASML is expected to start supplying high-NA machines for mass production next year. ASML has previously printed the first images at 10nm, or 20nm, but they involved “simple” straight lines rather than more complex chip structures.
The dimensions listed here do not correspond to the “nanometer” used to refer to the processes used by chipmakers like Intel, Samsung, and TSMC. The actual dimensions of transistors have long deviated from the brand names used by chipmakers. Tweakers published a backstory on this in 2017.
